1. Field of the Invention
The present invention relates to a charge coupled device (CCD), and more particularly, to a method for fabricating a CCD image sensor.
2. Discussion of the Related Art
Generally, a solid-state image sensor includes a plurality of photoelectric conversion regions, a plurality of vertical charge transfer regions, a horizontal charge transfer region, and a floating diffusion region. The photoelectric conversion regions are disposed at a predetermined interval in a matrix arrangement and convert an optical signal to an electrical signal to produce image charges. The vertical charge transfer regions are formed between the respective photoelectric conversion regions in vertical direction and transfer the image charges produced in the photoelectric conversion regions in vertical direction. The horizontal charge transfer region transfers the image charges transferred in the vertical direction in horizontal direction. The floating diffusion region senses the image charges transferred in the horizontal direction and outputs them to peripheral circuits.
FIG. 1a is a plan view of a conventional floating diffusion. FIG. 1b is a sectional view of a conventional floating diffusion taken along II--II line of FIG. 1a.
The floating diffusion FD is formed at the end of the horizontal charge transfer region and includes a P-well 12, a buried charge coupled device (BCCD) 13, an offset gate (OG) 14, a floating diffusion region 15, a reset drain region 16, a reset gate 17, and a charge detector. The P-well 12 is formed on a surface of an N type substrate 11. The BCCD 13 is formed in a surface of the P-well 12. The offset gate 14 is formed at a top portion of the end of the BCCD 13 and transfers charges transferred to the end of the BCCD 13. The floating diffusion region 15 is formed at the end of the BCCD 13 and senses the charges transferred through the offset gate 14. The reset drain region 16 is formed at one side of the floating diffusion region 15 and resets the sensed charges. The reset gate 17 is formed at a top portion between the floating diffusion region 15 and the reset drain region 16 and transfers the sensed charges to the reset drain region 16. The charge detector (not shown) is formed of transistors which are connected to a floating gate 18 of the floating diffusion region 15 to sense the charges.
In the aforementioned conventional floating diffusion, a current flows from the floating diffusion region 15 to the reset drain region 16 if a bias is applied to the reset gate 17 and the reset drain region 16.
A method for fabricating the conventional CCD image sensor will be described with reference to FIG. 2a to FIG. 2f.
FIG. 2a to FIG. 2f are sectional views illustrating fabricating process steps of a conventional CCD image sensor.
As illustrated in FIG. 2a, a P-well 22 is formed on a surface of an N type semiconductor substrate 21. Ions are implanted into a predetermined region of the P-well 22 to form a BCCD 23 which is used as a horizontal charge transfer channel.
A gate oxide film 24 and a nitride film 25 for a gate insulation are sequentially formed on an entire surface of the N type semiconductor substrate 21 including the BCCD 23. A polysilicon 26 is formed on the nitride film 25. A first photoresist 27 is deposited on the polysilicon 26 and patterned by exposure and developing processes.
As illustrated in FIG. 2b, the polysilicon 26 is selectively removed using the patterned first photoresist 27 as a mask to form an offset gate 26a and a reset gate 26b.
Subsequently, an oxide film 28 is formed on the entire surface of the N type semiconductor substrate including the offset gate 26a and the reset gate 26b. The oxide film 28 is selectively removed to remain at top portions and side portions of the offset gate 26a and the reset gate 26b.
As illustrated in FIG. 2c, a second photoresist 29 is deposited on the entire surface of the N type semiconductor substrate 21 including the oxide film 28 and patterned by exposure and developing processes.
The nitride film 25 is then selectively removed using the patterned second photoresist 29 as a mask to partially expose a surface of the gate oxide film 24.
Thereafter, impurity ions are implanted into the entire surface of the N type semiconductor substrate 21 using the patterned second photoresist 29 as a mask to form a floating diffusion region 30 for ohmic contact in a predetermined region of the BCCD 23.
As illustrated in FIG. 2d, the second photoresist 29 is removed. A third photoresist 31 is deposited on the entire surface of the N type semiconductor substrate 21 and patterned by exposure and developing processes.
Subsequently, the gate oxide film 24 is selectively removed using the patterned photoresist 31 as a mask to partially expose a surface of the floating diffusion region 30, so that a contact hole 32 is formed.
As illustrated in FIG. 2e, the third photoresist 31 is removed. A metal layer 33 is formed on the entire surface of the N type semiconductor substrate 21 including the contact hole 32. A fourth photoresist 34 is deposited on the metal layer 33 and then patterned by exposure and developing processes.
As illustrated in FIG. 2f, the metal layer 33 is patterned using the patterned fourth photoresist 34 as a mask to ohmic contact with the floating diffusion region 30. As a result, a floating gate 33a is formed. The floating gate 33a outputs image charges in the contact hole 32 and at a top portion of the nitride film 25 adjacent to the contact hole 32 to peripheral circuits (not shown).
Generally, overall charges produced by light can be expressed as Qsig=Cin*Vout, where Cin is overall capacitance applied to the floating diffusion region through a sensing amplifier and Vout is a sensing voltage in the floating diffusion region.
In addition, Vout=Qsig/Cin can be achieved by the above expression. In this case, the larger Cin is, the lower the sensing voltage of the floating diffusion region is.
The conventional method for fabricating a CCD has a problem.
That is, since the floating gate is widely formed around the contact hole including the contact hole to avoid misalignment of the floating gate which is used for ohmic contact with the floating diffusion region, parasitic capacitance occurs in the floating diffusion region. As a result, there results in limitation in increasing the sensing voltage of the floating diffusion.